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RM0008
General-purpose timer (TIMx)
In the following example, the upcounter is incremented at each rising edge of the ETR signal
as soon as a rising edge of TI1 occurs:
1.
Configure the external trigger input circuit by programming the TIMx_SMCR register as
follows:
–
–
–
ETF = 0000: no filter
ETPS=00: prescaler disabled
ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock
mode 2.
2.
Configure the channel 1 as follows, to detect rising edges on TI:
–
–
–
–
IC1F=0000: no filter.
The capture prescaler is not used for triggering and does not need to be
configured.
CC1S=01in TIMx_CCMR1 register to select only the input capture source
CC1P=0 in TIMx_CCER register to validate the polarity (and detect rising edge
only).
3.
Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on
ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is
due to the resynchronization circuit on ETRP input.
Figure 138. Control circuit in external clock mode 2 + trigger mode
TI1
CEN/CNT_EN
ETR
Counter clock = CK_CNT = CK_PSC
Counter register
34
35
36
TIF
14.3.15
Timer synchronization
The TIMx timers are linked together internally for timer synchronization or chaining. When
one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of
another Timer configured in Slave Mode.
The following figure presents an overview of the trigger selection and the master mode
selection blocks.
Doc ID 13902 Rev 9
349/995
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